Expertise
Areas of Specialization
Research Clusters
Current status
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Accepting graduate students
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Assistant Professor
Electrical & Computer Engineering
Overview
My passion lies in crafting high-performance application-specific computing systems. At present, my focus revolves around delving into hardware-level strategies to optimize the efficiency of machine learning platforms and applications. Simultaneously, I am actively engaged in exploring hardware-efficient machine learning techniques tailored to the realm of neurotechnology. Notably, I have recently been collaborating closely with neuroscientists to develop digital processing hardware methods for brain-computer interfacing.
As I look ahead, my research trajectory is set to encompass a thorough investigation of hardware-efficient domain-specific acceleration, with a specific emphasis on machine learning and neuroscience applications. This entails harnessing the capabilities of hybrid platforms like FPGAs and ASICs to function as spatially parallel accelerators. The goal is to implement hardware-efficient domain-specific architectures that offer a harmonious blend of high-level programmability, configurability, cost-effectiveness, power efficiency, and performance. Another exciting dimension of my future research involves the development of remarkably efficient hardware architectures to cater to the intricate demands of brain data analysis and decoding.
Beyond these primary pursuits, my research interests span a broad spectrum, including:
- Advancements in hardware-efficient deep learning and its versatile applications,
- Innovations within the domain of neurotechnology and brain-computer interfaces,
- Exploration of architectures within massively parallel reconfigurable systems,
- Refinement of CAD algorithms aimed at streamlining VLSI physical design automation, and
- In-depth investigation into asynchronous circuits and the effective management of clock domain crossings.
By embarking on these avenues of research, my goal is to push the boundaries of engineering innovation, contribute significantly to various fields of interest, and make a lasting impact on the advancement of technology.
Ameer M. S. Abdelhadi is an assistant professor of Computer Engineering in the Department of Electrical and Computer Engineering at McMaster University. He obtained his PhD in Computer Engineering from the University of British Columbia in 2016. Prior to joining McMaster, Dr. Abdelhadi held various academic positions as a research fellow and lecturer at the University of Toronto, Imperial College London, and Simon Fraser University. Before pursuing his graduate studies, he held multiple design and research positions in the semiconductor industry. Dr. Abdelhadi’s research interests span multiple areas, including application-specific custom-tailored computer architecture and hardware acceleration, hardware-efficient deep learning, neurotechnology, reconfigurable computing, and asynchronous circuits.
Ph.D. The University of British Columbia (UBC)
Best Paper Award; The 2017 IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC ‘2017)
Refereed Publications (Selected; Last updated in August 2023):
R. Gulve, N. Sarhangnejad, G. Dutta, M. Sakr, D. Nguyen, R. Rangel, W. Chen, Z. Xia, M. Wei, N. Gusev, E. Lin, X. Sun, L. Hanxu, N. Katic, A. Abdelhadi, A. Moshovos, K. Kutulakos, and R. Genov,
“39000-Subexposures/s Dual-ADC CMOS Image Sensor with Dual-Tap Coded-Exposure Pixels for Single-Shot HDR and 3D Computational Imaging,”
in IEEE Journal of Solid-State Circuits (JSSC), 2023.
A. M.S. Abdelhadi, E. Sha, and A. Moshovos,
“A Massive-Scale Brain Activity Decoding Chip,”
in Proceedings of the 2022 IEEE Hot Chips Symposium (HCS ‘2022), August 2022.
R. Gulve, N. Sarhangnejad, G. Dutta, M. Sakr, D. Nguyen, R. Rangel, W. Chen, Z. Xia, M. Wei, N. Gusev, E. Lin, X. Sun, L. Hanxu, N. Katic, A. Abdelhadi, A. Moshovos, K. Kutulakos, and R. Genov,
“A 39,000 Subexposures/s CMOS Image Sensor with Dual-tap Coded-exposure Data-memory Pixel for Adaptive Single-shot Computational Imaging,”
in Proceedings of the 2022 IEEE Symposium on VLSI Technology and Circuits, June 2022.
A. Hadi Zadeh, M. Mahmoud, A. M.S. Abdelhadi, and A. Moshovos,
“Mokey: Enabling Narrow Fixed-Point Inference for Out-of-the-Box Floating-Point Transformer Models,”
in Proceedings of the 2022 ACM/IEEE 49th Annual International Symposium on Computer Architecture (ISCA-49 ‘2022), June 2022.
A. M.S. Abdelhadi, E. Sha, C. Bannon, M. Mahmoud, H. Steenland, and A. Moshovos,
“Noema: Hardware-Efficient Template Matching for Neural Population Pattern Detection,”
in Proceedings of the 2021 54th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-54 ‘2021), October 2021.
A. M.S. Abdelhadi and H. Li,
“Enabling Mixed-Timing NoCs for FPGAs: Reconfigurable Synthesizable Synchronization FIFOs,”
in Proceedings of the 2021 International Conference on Field-Programmable Logic and Applications (FPL ‘2021), August 2021.
H. Li, A. M.S. Abdelhadi, R. Shi, J. Zhang, and Q. Liu,
“Adversarial Hardware with Functional and Topological Camouflage,”
in Proceedings of the 2021 IEEE International Symposium on Circuits and Systems (ISCAS ‘2021), May 2021.
A. M.S. Abdelhadi and H. Li,
“Reconfigurable Synthesizable Synchronization FIFOs,”
in Proceedings of the 2021 IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM ‘2021), May 2021.
I. E. Vivancos, S. Sharify, D. Ly-Ma, A. M.S. Abdelhadi, C. Bannon, M. Nikolic, M. Mahmoud, A. D. Lascorz, G. Pekhimenko, and A. Moshovos,
“Boveda: Building an On-Chip Deep Learning Memory Hierarchy Brick by Brick,”
in Proceedings of the 2021 conference on Machine Learning and Systems (MLSys ‘2021), April 2021.
H. Li, A. M.S. Abdelhadi, R. Shi, J. Zhang, and Q. Liu,
“Adversarial Hardware with Functional and Topological Camouflage,”
in IEEE Transactions on Circuits and Systems II (TCAS-II), vol. 68, no. 5, pp. 1685-1689, May 2021.
A. M.S. Abdelhadi,
“Synthesizable Synchronization FIFOs Utilizing the Asynchronous Pulse-Based Handshake Protocol,”
in Proceedings of the 2020 IEEE Nordic Circuits and Systems Conference (NorCAS ‘2020), October 2020.
A. M.S. Abdelhadi,
“High-Throughput Synthesizable Synchronization FIFOs for Mixed-Timing NoCs,”
in Proceedings of the 53rd 2020 Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-53 ‘2020): 13th International Workshop on Network on Chip Architectures (NoCArc ‘2020), October 2020.
A. M.S. Abdelhadi, C. S. Bouganis, and G. A. Constantinides,
“Accelerated Approximate Nearest Neighbors Search Through Hierarchical Product Quantization,”
in Proceedings of the 2019 International Conference on Field-Programmable Technology (ICFPT ‘2019), December 2019.
A. M.S. Abdelhadi, and L. Shannon,
“Revisiting Deep Learning Parallelism: Fine-Grained Inference Engine Utilizing Online Arithmetic,”
in Proceedings of the 2019 International Conference on Field-Programmable Technology (ICFPT ‘2019), December 2019.
A. M.S. Abdelhadi, Y. Zhang, D. Chen, G. Datta, P. Beerel, and M.R. Greenstreet
“Two-Phase Asynchronous to Synchronous Interfaces with Early Synchronization for an Open-Source Bundled Data Flow,”
in Proceedings of the 2019 IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC ‘2019), May 2019.
A. M.S. Abdelhadi, G. G.F. Lemieux, and L. Shannon,
“Modular Block-RAM-Based Longest-Prefix Match Ternary Content-Addressable Memories,”
in Proceedings of the 2018 International Conference on Field-Programmable Logic and Applications (FPL ‘2018), August 2018.
A. M.S. Abdelhadi, D. H. Noronha, S. J.E. Wilton, and L. Shannon,
“Deep Neural Networks Benchmark Suite for FPGAs Utilizing a TensorFlow to Routing High-Level Synthesis ,”
in Proceedings of the 2018 Computing Hardware for Emerging Intelligent Sensory Applications (COHESA ‘2018), Toronto, Ontario, July 2018.
A. M.S. Abdelhadi and M. R. Greenstreet,
“Interleaved Architectures for High-Throughput Synthesizable Synchronization FIFOs,”
in Proceedings of the 2017 IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC ‘2017), May 2017. (Best paper award winner)
A. M.S. Abdelhadi and G. G.F. Lemieux,
“A Multi-Ported Memory Compiler Utilizing True Dual-port BRAMs,”
in Proceedings of the 2016 IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM ‘2016), May 2016. (Best paper candidate)
A. M.S. Abdelhadi and G. G.F. Lemieux,
“Modular Switched Multi-ported SRAM-based Memories,”
in ACM Transactions on Reconfigurable Technology and Systems (TRETS) Special Issue on Reconfigurable Components with Source Code, accepted in Jul. 2015. 27 pages. (Invited)
A. M.S. Abdelhadi and G. G.F. Lemieux,
“Modular SRAM-based Binary Content-Addressable Memories,”
in Proceedings of the 2015 IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM ‘2015), May 2015.
A. M.S. Abdelhadi and G. G.F. Lemieux,
“Deep and Narrow Binary Content-Addressable Memories using FPGA-based BRAMs,”
in Proceedings of the 2014 International Conference on Field-Programmable Technology (ICFPT ‘2014), December 2014.
A. M.S. Abdelhadi and G. G.F. Lemieux,
“Modular Multi-Ported SRAM-based Memories,”
in Proceedings of the 2014 ACM/SIGDA International Symposium on Field-programmable Gate Arrays (FPGA ‘2014), February 2014. (Best paper candidate)
A. M.S. Abdelhadi, R. Ginosar, A. Kolodny, and E. G. Friedman,
“Timing-Driven Variation-Aware Synthesis of Hybrid Mesh/Tree Clock Distribution Networks,”
in INTEGRATION, the VLSI journal (2013).
A. Brant, A. M.S. Abdelhadi, A. Severance, T. Tang, M. Yue, and G. G.F. Lemieux,
“Safe Overclocking of Tightly Coupled CGRAs and Processor Arrays using Razor,”
in Proceedings of the 2013 IEEE intl. Conf. on Field-Programmable Custom Computing Machines (FCCM ‘2013), April 2013.
A. M.S. Abdelhadi, T. Ono, B. Quinton, and M. R. Greenstreet,
“Cell-based Modular mixed-timing Synchronizing FIFOs,”
in Proceeding of the IEEE/ACM 2012 International Conference on Computer-Aided Design (ICCAD ’12): Workshop on CAD for Multi-Synchronous and Asynchronous Circuits and Systems, San Jose, CA, November 2012.
A. Brant, A. M.S. Abdelhadi, A. Severance, and G. G.F. Lemieux,
“Pipeline frequency boosting: Hiding dual-ported block RAM latency using intentional clock skew,”
in Proceedings of the IEEE International Conference on Field-Programmable Technology (FPT ‘2012), December 2012.
A. M.S. Abdelhadi and G. G.F. Lemieux,
“Configuration Bitstream Reduction for SRAM-based FPGAs by Enumerating LUT Input Permutations,”
in Proceedings of the International Conference on Reconfigurable Computing and FPGAs (Reconfig ‘2011), pp. 20-26, Dec. 2011.
A. M.S. Abdelhadi, R. Ginosar, A. Kolodny, and E. G. Friedman,
“Synthesis of Variation-Aware Hybrid Clock Distribution Networks,”
in Proceedings of the International Conference of the Israeli Semiconductor Industry (ChipEx ’10), June 2010.
A. M.S. Abdelhadi, R. Ginosar, A. Kolodny, and E. G. Friedman,
“Timing-Driven Variation-Aware Nonuniform Clock Mesh Synthesis,”
in Proceedings of the ACM/IEEE Great Lakes Symposium on VLSI (GLSVLSI ’10), pp. 15-20, May 2010.
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